unisonic technologies co., ltd ccvga7c9 preliminary tvs www.unisonic.com.tw 1 of 6 copyright ? 2013 unisonic technologies co., ltd qw-r223-015.a vga or dvi-i port companion circuit ? description the utc ccvga7c9 is an esd solution for the vga or dvi-i port connector. this device integrates esd protection for all signals, level shifting for the ddc signals and buffering for the sync signals. esd protection for the video, ddc and sync lines is implemented with low-capacitance current steering diodes. separate positive supply rails are provided for the video, ddc and sync channels to facilitate interfacing with low voltage video controller ics to provide design flexibility in multi-supply-voltage environments. two non-inverting drivers provide buffering for the hsync and vsync signals from the video controller ic (sync1, sync2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc_sync , which is typically 5v. additionally, each driver has a series termination resistor (r t ) connected to the sync_out pin, elimin ating the external termination resistor s typically required for the hsync and vsync lines of the video cable. there are three versions with different values of rt to allow termination at typically 65 ? (utc ccvga7c9 ? 00) or 15 ? (utc ccvga7c9 ? 02). two n-channel mosfets provide the level shifting func tion required when the ddc controller is operated at a lower supply voltage than the monitor. the gate terminals for the mosfets (v cc_ddc ) should be connected to the supply rail (typically 3.3 v) that supplies powe r to the transceivers of the ddc controller. all esd diodes are designed to safely handle the high cu rrent spikes specified by iec-61000-4-2 level 4 (8kv contact discharge if c byp is present, 4kv if not). the esd protec tion for the ddc signal pins are designed to prevent ?back current? when the device is powered down while connected to a monitor that is powered up. ? features * 7 channels of esd protection for all vga port connector pins meeting iec-61000-4-2 level 4 esd requirements (8kv contact discharge) * includes esd protection, level-shifting, buffering and sync impedance matching * very low loading capacitance from esd protection diodes on video lines (4pf maximum) * 5v drivers for hsync and vsync lines * integrated impedance matching resistors on sync lines * bi-directional level shifting n-channel fets provided for ddc_clk & ddc_data channels * backdrive protection on ddc lines ? ordering information ordering number package packing lead free halogen free ccvga7c9l-r16-t CCVGA7C9G-R16-T ssop-16 tube ccvga7c9l-r16-r ccvga7c9g-r16-r ssop-16 tape reel
ccvga7c9 preliminary tvs unisonic technologies co., ltd 2 of 6 www.unisonic.com.tw qw-r223-015.a ? pin configuration ? pin description pin no. pin name description 1 v cc_sync this is an isolated supply input for the sync_1 and sync_2 level shifters and their associated esd protection circuits. 2 v cc_video this is a supply pin specifically for the video_1, video_2 and vi deo_3 esd protection circuits. 3 video_1 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 4 video_2 5 video_3 6 gnd ground. 7 v cc _ ddc this is an isolated supply input for the ddc_1 and ddc_2 level-shifting n-fet gates. 8 byp this input is using a 0.2uf bypass capaci tor will increase the esd robustness of the system. 9 ddc_out1 ddc signal output. connects to the video connector side of one of the sync lines 10 ddc_in1 ddc signal input. connects to the vga cont roller side of one of the sync lines. 11 ddc_in2 12 ddc_out2 ddc signal output. connects to the video connector side of one of the sync lines. 13 sync_in1 sync signal buffer input. connects to t he vga controller side of one of the sync lines. 14 sync_out1 sync signal buffer output. connects to the video connector side of one of the sync lines. 15 sync_in2 sync signal buffer input. connects to t he vga controller side of one of the sync lines. 16 sync_out2 sync signal buffer output. connects to the video connector side of one of the sync lines.
ccvga7c9 preliminary tvs unisonic technologies co., ltd 3 of 6 www.unisonic.com.tw qw-r223-015.a ? block diagram
ccvga7c9 preliminary tvs unisonic technologies co., ltd 4 of 6 www.unisonic.com.tw qw-r223-015.a ? absolute maximum rating parameter symbol ratings unit v cc_video , v cc_ddc and v cc_sync supply voltage inputs v cc_video , v cc_ddc , v cc_sync [gnd-0.5]~+6.0 v esd diode forward current (one diode conducting at a time) 10 ma dc voltage at inputs video_1, video_2, vi deo_3 [gnd-0.5]~[v cc _ video +0.5] v ddc_in1, ddc_in2 [gnd-0.5]~6.0 v ddc_out1, ddc_out2 [gnd-0.5]~6.0 v sync_in1, sync_in2 [gnd-0.5]~[v cc _ sync +0.5] v operating temperature range t opr -40~+85 c storage temperature t stg -40~+150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (note 1) parameter symbol test conditions min typ max unit v cc_video supply current i cc_video v cc_video =5.0v, video inputs at v cc _ video or gnd 10 a v cc _ ddc supply current i cc _ ddc v cc _ ddc =5.0v 10 a v cc_sync supply current i cc_sync v cc_sync =5v, sync inputs at gnd or v cc _ sync , sync outputs unloaded 50 a v cc_sync =5v, sync inputs at 3.0 v, sync outputs unloaded 2.0 ma esd diode forward voltage v f i f =10ma 1.0 v logic high input voltage v ih v cc _ sync =5.0v, (note 2) 2.0 v logic low input voltage v il v cc _ sync =5.0v, (note 2) 0.6 v logic high output voltage v oh i oh =0ma, v cc _ sync =5.0v, (note 2) 4.85 v logic low output voltage v ol i ol =0ma, v cc _ sync =5.0v, (note 2) 0.15 v sync driver output resistance (ccvga7c9 ? 00 only) r out v cc_sync =5.0v, sync inputs at gnd or 3.0v 65 ? sync driver output resistance (ccvga7c9 ? 02 only) r out v cc_sync =5.0v, sync inputs at gnd or 3.0v, (note 2) 15 ? logic high output voltage (ccvga7c9 ? 02 only) v oh ? 02 i oh =24ma, v cc_sync =5.0v, (note 2) 2.0 v logic low output voltage (ccvga7c9 ? 02 only) v ol ? 02 i ol =24ma, v cc_sync =5.0v, (note 2) 0.8 v input current video inputs i in v cc _ video =5.0v, v in =v cc _ video or gnd 1 a sync_in1, sync_in2 inputs v cc _ sync =5.0v, v in =v cc _ sync or gnd 1 a level shifting n ? mosfet ?off? state leakage current i off (v cc_ddc - v ddc_in ) 0.4v, v ddc _ out =v cc _ ddc 10 a (v cc_ddc - v ddc_out ) 0.4v, v ddc _in = v cc _ ddc 10 a voltage drop across level-shifting n-mosfet when ?on? v on v cc_ddc =2.5v, v s =gnd, i ds =3ma 0.18 v video input capacitance (note 3) c in_vid v cc _ video =5.0v, v in =2.5v, f=1mhz 4 pf v cc _ video =2.5v, v in =1.25v, f=1mhz 4.5 pf sync driver l => h propagation delay t plh c l =50pf, v cc =5.0v, input tr and tf 5ns 12 ns
ccvga7c9 preliminary tvs unisonic technologies co., ltd 5 of 6 www.unisonic.com.tw qw-r223-015.a ? electrical characteristics(cont.) parameter symbol test conditions min typ max unit sync driver h => l propagation delay t phl c l =50pf, v cc =5.0v, input t r and t f 5ns 12 ns sync driver output rise & fall times t r , t f c l =50pf, v cc =5.0v, input t r and t f 5ns 4 ns esd withstand voltage (note 3) v esd v cc _ video =v cc _ sync =5v 8 kv notes: 1. all parameters specified over standa rd operating conditions unless otherwise noted. 2. these parameters apply only to the sync drivers. note that r out =r t + r buffer . 3. the sync_out pins on the utc ccvga7c9 -02 are guaranteed for 2kv hbm esd protection.
ccvga7c9 preliminary tvs unisonic technologies co., ltd 6 of 6 www.unisonic.com.tw qw-r223-015.a ? typical application circuit vf vf vf notes: 1. the utc ccvga7c9 should be placed as close to the vga or dvi ? i connector as possible. 2. the esd protection channels vide o_1, video_2, video_3 may be used interchangeably between the r, g, b signals. 3. if differential video signal routing is used, the red, blue, and green signal lines should be terminated with external 37.5 ? resistors. 4. ?vf? are external video filters for the rgb signals. 5. the ddc level shifters ddc_in, ddc_out, may be used interchangeably between ddca_clk and ddca_data. 6. the sync buffers may be used interchangeably between hsync and vsync. utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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